X
X
R
R
P
P
7
7
7
7
0
0
8
8
a
a
n
n
d
d
X
X
R
R
P
P
7
7
7
7
4
4
0
0
Q
Q
u
u
a
a
d
d
C
C
h
h
a
a
n
n
n
n
e
e
l
l
D
D
i
i
g
g
i
i
t
t
a
a
l
l
P
P
W
W
M
M
S
S
t
t
e
e
p
p
D
D
o
o
w
w
n
n
C
C
o
o
n
n
t
t
r
r
o
o
l
l
l
l
e
e
r
r
s
s
?2012 Exar Corporation
23/28
Rev. 1.2.2
GPIO Pins Polarity
The polarity of the GPIO pin can be set by using the GPIO_ACT_POL register. This register allows
any GPIO pin whether configured as an input or output to change polarity. Bits [5:0] are used to
set the polarity of GPIO 0 though 5. If the IC operates in I
2
C mode, then the commands for Bits
[5:4] are ignored.
Supply Rail Enable
Each GPIO can be configured to enable a specific power rail for the system. The GPIOx_CFG
register allows a GPIO to enable/disable any of the following rails controlled by the chip:
" A single buck power controller
" The Standby LDO
" Any mix of the Standby LDO and power controller(s)
When the configured GPIO is asserted externally, the corresponding rails will be enabled, and they
will be similarly disabled when the GPIO is de-asserted. This supply enabling/disabling can also be
controlled through the I
2
C interface.
Power Good Indicator
The GPIO pins can be configured as Power Good indicators for one or more rails. The GPIO pin is
asserted when all rails configured for this specific IO are within specified limits for regulation. This
information can also be found in the READ_PWRGD_SS_FLAG status register.
Fault and Warning Indication
The GPIOs can be configured to signal Fault or Warning conditions when they occur in the chip.
Each GPIO can be configured to signal one of the following:
" OCP Fault on Channel 1 - 4
" OCP Warning on Channel 1 - 4
" OVP Fault on Channel 1 - 4
" UVLO Fault on VIN1 or VIN2
" UVLO Warning on VIN1 or VIN2
" Over Temperature Fault or Warning
I
2
C COMMUNICATION
The I
2
C communication is standard 2-wire communication available between the Host and the IC.
This interface allows for the full control, monitoring, and reconfiguration of the semiconductor.
Each device in an I
2
C-bus system is activated by sending a valid address to the device. The address
always has to be sent as the first byte after the start condition in the I
2
C -bus protocol
MSB
6
5
4
3
2
1
0
R/W
LSB
Fig. 29: Alignment of I2C address in 8 bit byte
There is one address byte required since 7-bit addresses are used. The last bit of the address byte
is the read/write-bit and should always be set according to the required operation. This 7-bit I
2
C
address is stored in the NVM. One can program a blank device with the 7-bit Slave address or
select one of the preprogrammed options. The 7-bit address plus the R/W bit create an 8-bit data
value that is sent on the bus.
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相关PDF资料
ZDS1009TA
IC CURRENT MIRROR SOT223-8
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ZXCT1009T8TA
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